In conventional nonvolatile semiconductor memory devices (memory), elements have been integrated in a two-dimensional plane on a silicon substrate. Although the dimensions of one element have been reduced (downscaled) to increase the storage capacity of memory, such downscaling in recent years has become difficult in regard to both cost and technology.
Conversely, collectively patterned three-dimensionally stacked memory has been proposed. Such a collectively patterned three-dimensionally stacked memory includes a stacked body having insulating films alternately stacked with electrode films, silicon pillars piercing the stacked body, and charge storage layers (memory layers) between the silicon pillars and the electrode films. Thereby, memory cells are provided at the intersections between the silicon pillars and each of the electrode films.
Further, JP-A 2009-146954 (Kokai) discloses a configuration using a memory string having a U-shaped configuration made by connecting two silicon pillars on the substrate side. By using such a U-shaped memory string, for example, the degrees of freedom of the material used in the charge storage layer can be increased.
However, there is room for improvement to further increase productivity and operational stability.